This application claims the priority of Korean Patent Application No. 2003-79901, filed on Nov. 12, 2003, in the Korean Intellectual Property Office. The entire disclosure of Korean Patent Application No. 2003-79901 is hereby incorporated herein by reference.
1. Field of the Invention
The present invention relates to devices and methods for electrically testing semiconductor memory devices, and more particularly to methods and devices for electrically testing flash memory devices.
2. Description of the Related Art
Prior to sale, semiconductor devices are tested and screened to determine if defects were produced during the fabricating process. The devices are tested and screened after completing the wafer fabricating process and/or after the package assembly process.
Test systems measure Direct Current (DC), measure Alternating Current (AC), and test the functional characteristics of the semiconductor devices. Testing semiconductor memory devices demands high throughput, i.e., high productivity. Therefore, most makers of semiconductor memory devices use parallel test systems rather than serial test systems.
Serial test systems perform tests on a one by one basis. Parallel testing simultaneously tests many devices at the same time, thus, enhancing the throughput. In many of the presently available testers, the number of Devices Under Test (DUT) that can be simultaneously tested in parallel is 256.
FIG. 1 is a block diagram schematically showing a conventional tester used to an electrically test semiconductor memory devices.
The tester 90 includes a test processor 10. A programmable power supply 20 is connected to and controlled by the test processor 10. A DC parameter measurement unit 30 and an algorithmic pattern generator 40 are also connected to and controlled by the test processor 10. The algorithmic pattern generator 40 has a first memory 42 for storing failure information. A timing generator 50 and pin electronics 70 are also connected to and controlled by the test processor 10. Pin electronics 70 includes a driver 72 and a comparator 74. A wave shape formatter 60 processes information supplied from the algorithmic pattern generator 40 and the timing generator 50 to supply the processed information to the pin electronics 70. The reference numeral 80 designates one or more DUTs.
FIG. 2 is a block diagram showing how the memories of the DUTs are mapped to the first memory 42 while flash memory devices are subjected to the electrical test. Referring to FIG. 2, the system operates as follows. The tester 90 starts to sequentially test the DC, AC and function characteristics of the DUTs 80 so as to electrically test the flash memory device. The system illustrated is a parallel test system, in which a plurality of DUTs 80a, 80b, 80c, 80d, . . . , and 80n are simultaneously tested.
The memory 42 is generally referred to as a Failure Analysis Memory (FAM) or an Error Catch RAM (ECR). It stores failure information when failures occurs during the function test. The memory 42 is constructed to correspond to a memory map of respective DUTs 80a, 80b, 80c, 80d, . . . , and 80n. Thus, if the failure occurs in the 100th address in the memory of the first DUT 80a, failure information is stored in the 100th address of memory 42, which is associated with the first DUT 80a in the tester.
The information stored in the memory 42 is used as expected data when a write operation or a read operation is simultaneously executed in the plurality of DUTs 80a, 80b, 80c, 80d, . . . , and 80n. 
Since conventional semiconductor memory testers have only a single memory 42, and this memory stores the failure information generated in the DUTs 80a, 80b, 80c, 80d, . . . , and 80n, only the same data can be transferred to the plurality of DUTs 80a, 80b, 80c, 80d, . . . , and 80n. Thus, tests such as a trim test, a repair test, and an invalid block masking test can not be performed on such a tester. Such tests must be individually performed with respect to each of the DUTs 80a, 80b, 80c, 80d, . . . , and 80n since they have different failure addresses. With conventional testers, such tests must, in general, be performed by a serial test system.
An example of a system that conducts electrical tests of semiconductor memory devices and which has only a single memory is shown in U.S. Pat. No. 5,896,398 (issued in Apr. 20, 1999).
FIG. 3 is a block diagram illustrating a prior art method of electrically testing flash memory devices. FIG. 4 is a flowchart illustrating a method of electrically testing the flash memory device according to conventional techniques.
Referring to FIGS. 3 and 4, electrical tests of the flash memory devices are conducted by a parallel test system. The test generally includes a pin contact test (SI 0 in FIG. 4), a DC characteristic test (S20), a function test & an AC characteristic test (S30) and pass/reject sorting (S40). All tests are executed by the parallel test system and they have a relatively high throughput when the number of DUTs is in the order of 256 devices. However, in order to conduct tests such as an invalid block masking test, the electrical test is conducted serially. Such a test involves searching for failure information in the memory 42 on a one by one basis (see FIG. 3) without carrying out the parallel test. Consequently, the electrical test is shifted from a parallel system to a serial system. This extends the test time and degrades test efficiency.